1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to an improved transistor and a method for forming an improved transistor having an ultra thin, high K value, gate dielectric.
2. Description of the Related Art
Fabrication of a metal oxide semiconductor field-effect transistor (MOSFET) device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d) material over a relatively thin gate oxide. The polysilicon material and the gate oxide are then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor serves to self-align impurities forwarded into the substrate on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant species. If the impurity dopant species used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (xe2x80x9cn-channelxe2x80x9d) transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET (xe2x80x9cp-channelxe2x80x9d) transistor device. Integrated circuits use either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. The combination of an n-channel and a p-channel device on a single substrate is termed a complementary MOS (xe2x80x9cCMOSxe2x80x9d) device.
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to reduce the transistor threshold voltage, VT. Several factors contribute to VT, one of which is the gate-to-substrate capacitance. VT of a transistor decreases as the gate-to-substrate capacitance increases. The capacitance per unit area, Cox, of a gate dielectric can be expressed as:
Cox=∈/tox
where ∈ is the permittivity the gate oxide and tox is the thickness of the gate oxide. The above equation for Cox demonstrates that the capacitance between two layers of conductive material separated by a dielectric is directly proportional to the permittivity of the dielectric and inversely proportional to the thickness of the dielectric.
By normalizing the permittivity, ∈, of a material to the permittivity of vacuum, ∈o, the relative permittivity of a material can be determined. Relative permittivity, or dielectric constant, K, is typically used in place of permittivity. The dielectric constant of a material is defined as:
K=∈/∈o
Silicon dioxide (xe2x80x9coxidexe2x80x9d) has a relatively low K of approximately 3.7 to 3.8. Consequently, the minimum value of VT, and thus the transistor switching speed, is limited by the need to maintain a certain gate oxide thickness in order to promote capacitive coupling between the gate conductor and the substrate.
Because of the relationship between gate oxide thickness and threshold voltage, conventional transistors typically include an ultra thin gate oxide to increase the gate-to-substrate capacitance, and thereby lower VT. The value of the gate-to-source voltage, VGS, required to invert the channel underneath the gate conductor such that a drive current, ID, flows between the source and drain regions of the transistor is decreased. Consequently, the switching speed (from off to on and vice versa) of the logic gates of an integrated circuit employing such transistors is faster, allowing the integrated circuit to quickly transition between logic states (i.e., operate at high frequencies).
Unfortunately, thin oxide films may break down when subjected to an electric field. Particularly, for a gate oxide that is less than 50 xc3x85 thick, it is probable that when VGS is equivalent to only 3V, electrons can pass through the gate oxide by what is known as the quantum mechanical tunneling effect. In this manner, a tunneling current may undesirably form between the semiconductor substrate and the gate conductor, adversely affecting the operability of the device. It is postulated that these electrons may become entrapped within the gate oxide by, e.g., dangling bonds. Consequently, a net negative charge density may form in the gate oxide. As the trapped charge accumulates with time, VT may shift from its design specification. Breakdown of the gate oxide may also occur at even lower values of VGS because of defects in the gate oxide. Such defects are unfortunately prevalent in relatively thin gate oxides. For example, a thin gate oxide often contains pinholes and/or localized voids due to the unevenness at which the oxide grows on a less than perfect silicon lattice. Low breakdown voltages also correlate with high defect density near the surface of the substrate.
In addition, the gate electrode is typically made from deposited polysilicon (as stated above). To lower the resistivity of the polysilicon gate, and thus increase the speed of the transistor, it is desirable that the entire polysilicon layer forming the gate be substantially doped. During a conventional transistor formation process, the polysilicon gate is typically doped at the same time as the source/drain areas in order to make the process more efficient. This simultaneous implantation may cause difficulties since the implant depth required for the gate is typically deeper than the desired implant depth of the source/drain areas. Moreover, dopants residing in the gate conductor may eventually traverse the gate dielectric and enter the channel region, causing threshold skew. In particular, the boron commonly used to dope p+ gates readily migrates though a thin gate oxide (less than 125 angstroms) under high temperature processes (e.g., annealing at 900xc2x0 C.). In order to avoid this migration, processing temperatures must be lowered. Such lowering, however, may result in insufficient distribution and/or anneal of implanted dopants.
In order to resolve the problems described above, the use of a high-quality gate dielectric (i.e., one that is resistant to breakdown, has a high K value, etc.) is desired. High K value materials, such as silicon nitride (xe2x80x9cnitridexe2x80x9d), are sometimes used as the gate dielectric. Since nitride has a K value of about 8, a gate dielectric composed of nitride can be made thicker than a gate oxide while maintaining the equivalent gate-to-substrate capacitance. The increased thickness of a nitride gate dielectric relative to a similarly performing gate oxide helps to make the nitride gate dielectric more resistant to breakdown. Also, nitride is relatively impermeable to foreign species such as oxygen, and therefore provides an effective barrier against diffusion.
There are numerous problems, however, with many conventional techniques for implementing nitride gate dielectrics. Because of the mechanical stresses that develop at the silicon/silicon nitride interface, it is generally disadvantageous to deposit nitride directly upon a silicon wafer. Moreover, many methods of nitride deposition result in the formation of a nitride layer that is uneven, nonstoichiometric, and filled with pinholes. Such a nitride layer might contain, among other things, diffusion pathways through which dopants and electrons may undesirably pass.
Therefore, it would be desirable to develop a technique for fabricating a transistor composed of a high-quality gate dielectric. A high-quality gate dielectric would afford increased gate-to-substrate capacitance while being substantially resistant to breakdown. The improved technique would be one that avoids the problems of very thin oxides, yet provides high-speed operation necessary for modem integrated circuits. Tunneling currents formed between the gate dielectric and the gate conductor would be minimized along with the possibility of electrons becoming trapped within the gate dielectric. Migration of dopants from the gate electrode into the channel region would be substantially reduced over a conventional gate oxide. The transistor would thus be substantially resistant to threshold skews from the desired value of VT.
The problems identified above are in large part addressed by the technique hereof for forming an improved transistor. The present invention contemplates a transistor in which the gate dielectric layer includes a nitride layer. The nitride layer is formed by annealing a sacrificial polysilicon seed layer in a nitrogen-bearing ambient. The thickness of the polysilicon seed layer can easily be scaled to achieve precise control over the thickness of the nitride layer. Thermal growth of the nitride layer from the polysilicon seed layer preferably results in a nitride dielectric layer that has fewer electron traps than a deposited nitride layer. Because the K value of nitride is higher than that of oxide, a nitride gate dielectric that is thicker than a gate oxide can obtain similar capacitive coupling performance. In addition, thermally grown nitride is stoichiometric and contains strong Sixe2x80x94N bonds, which makes it an excellent diffusion barrier layer. The presence of the nitride layer beneath the gate electrode, therefore, helps prevent migration of dopants from the gate electrode into the channel region. Before the sacrificial polysilicon layer is annealed in a nitrogen-bearing ambient, it may be heated such that it is recrystallized. Recrystallization of the sacrificial polysilicon layer preferably increases the quality of any oxide or nitride layers grown from it. Preferably, the final gate dielectric is more resistant to breakdown and is more effective at preventing threshold skew than a comparatively thin deposited nitride gate dielectric or a conventional gate dielectric that only includes oxide.
According to one embodiment, the sacrificial polysilicon layer used to form the nitride is deposited upon a dielectric layer that covers a single crystal silicon substrate. As stated above, the silicon/silicon nitride interface is poor. Depositing silicon nitride directly onto a silicon surface creates high tensile stresses that can exceed the critical stress for dislocation generation in silicon. The dielectric layer, which may be composed of oxide, preferably serves as a buffer or xe2x80x9cpadxe2x80x9d to reduce these stresses. Moreover, the silicon/silicon oxide interface is well understood and, in terms of the amount of interface fixed charges and traps, superior to the silicon/silicon nitride interface. After growth or deposition, the dielectric layer may be etched to reduce its thickness. Preferably, the dielectric layer is thick enough to serve as a pad for the nitride layer, yet sufficiently thin that its lower K value (relative to nitride) does not negatively impact the overall gate-to-substrate capacitance of the final gate dielectric.
As stated above, growth of the nitride from the sacrificial polysilicon layer affords more control over the thickness of the nitride than do conventional deposition techniques. Depositing a uniformly thin nitride layer is difficult, and the resulting film typically has numerous pinholes. By annealing the polysilicon seed layer in a nitrogen-bearing ambient, a uniformly thin, high quality nitride layer may be formed. Forming the nitride layer includes the steps of depositing polysilicon, oxidizing an upper portion of the polysilicon, and etching the oxidized portion. These steps may be repeated until a desired thickness of the sacrificial polysilicon layer is achieved.
There are numerous benefits to recrystallizing the sacrificial polysilicon layer. Polysilicon thin films are made of small single crystal regions (grains) separated by grain boundaries. Although the grain boundaries are made up of disordered atoms, atoms within the grains are arranged in a periodic structure. Increasing the size of the grains within a layer of polysilicon advantageously allows its structure and properties to approach those of a layer of single crystal silicon. The structure and properties of polysilicon are highly dependent, among other things, on the temperature during deposition and any subsequent steps. By keeping the temperature below about 580xc2x0 C., polysilicon may be deposited in the amorphous phase. Temperatures above 580xc2x0 C. generally lead to deposition of polysilicon in the polycrystalline phase. Recrystallization of a deposited polysilicon layer causes growth of the size of grains and reduction of the extent of grain boundaries. Although higher deposition temperatures result in larger initial grain size, the final, post-recrystallization grain size tends to increase as deposition temperature decreases. In addition, the structural uniformity of a recrystallized amorphous layer is generally superior to that of a recrystallized polycrystalline silicon layer.
Another impetus for recrystallization is to improve the quality of any oxide or nitride layers grown from the sacrificial polysilicon layer. The breakdown strength of a thermally grown oxide or nitride layer is highly dependent on the smoothness of the surface of the polysilicon layer from which the layer is grown. Recrystallization of the sacrificial polysilicon layer, especially if it is deposited in the amorphous phase, may result in a substantial increase in the surface quality of the sacrificial polysilicon layer over a polysilicon layer that has not been recrystallized.
Broadly speaking, a method is presented for forming a transistor wherein polysilicon is preferably deposited upon a dielectric-covered substrate to form a sacrificial polysilicon layer. The sacrificial polysilicon layer may then be reduced to a desired thickness. Thickness reduction of the sacrificial polysilicon layer is preferably undertaken by oxidizing a portion of the sacrificial polysilicon layer and then etching the oxidized portion. The remaining sacrificial polysilicon layer may then be annealed in a nitrogen-bearing ambient such that it is converted to a gate dielectric layer that includes nitride. Non-sacrificial polysilicon may then be deposited upon the nitride-embodied gate dielectric layer, and select portions of the polysilicon may be removed to form a gate conductor. Lightly doped drain (xe2x80x9cLDDxe2x80x9d) and source/drain areas may be formed adjacent to the gate conductor.
According to another embodiment, a layer of oxide preferably is grown upon a single crystal silicon substrate. Growth of the layer of oxide may be undertaken in a nitrogen-bearing ambient such that the layer of oxide includes a substantial quantity of nitrogen atoms distributed throughout. A sacrificial polysilicon layer is then formed upon the layer of oxide. By varying the temperature at which the polysilicon is deposited, the sacrificial polysilicon layer may be formed in either an amorphous or a polycrystalline phase. A portion of the sacrificial polysilicon layer is preferably oxidized and etched away to reduce its thickness. The sacrificial polysilicon layer may be heated for recrystallization purposes. Annealing of the sacrificial polysilicon layer in a nitrogen-bearing ambient is preferably carried out such that the sacrificial polysilicon layer is converted into a layer of nitride. A gate structure may be patterned and LDD and source/drain areas formed. The final transistor preferably includes a gate dielectric with a high K value such that it provides good gate-to-substrate capacitive coupling without breakdown problems.